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NXP Semiconductors /MIMXRT1052 /DCP /CTRL_CLR

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Interpret as CTRL_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CHANNEL_INTERRUPT_ENABLE 0 (ENABLE_CONTEXT_SWITCHING)ENABLE_CONTEXT_SWITCHING 0 (ENABLE_CONTEXT_CACHING)ENABLE_CONTEXT_CACHING 0 (GATHER_RESIDUAL_WRITES)GATHER_RESIDUAL_WRITES 0 (Absent)PRESENT_SHA 0 (Absent)PRESENT_CRYPTO 0 (CLKGATE)CLKGATE 0 (SFTRST)SFTRST

PRESENT_SHA=Absent, PRESENT_CRYPTO=Absent

Description

DCP control register 0

Fields

CHANNEL_INTERRUPT_ENABLE

Per-channel interrupt enable bit

1 (CH0): CH0

2 (CH1): CH1

4 (CH2): CH2

8 (CH3): CH3
ENABLE_CONTEXT_SWITCHING

Enable automatic context switching for the channels
ENABLE_CONTEXT_CACHING

The software must set this bit to enable the caching of contexts between the operations
GATHER_RESIDUAL_WRITES

The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations
PRESENT_SHA

Indicates whether the SHA1/SHA2 functions are present.

0 (Absent): Absent

1 (Present): Present
PRESENT_CRYPTO

Indicates whether the crypto (cipher/hash) functions are present.

0 (Absent): Absent

1 (Present): Present
CLKGATE

This bit must be set to zero for a normal operation
SFTRST

Set this bit to zero to enable a normal DCP operation

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data